An IP module is a kind of integrated circuit, device or component with some specified function which is designed in advance and even has been verified. The foundry's self-developed IP module is often used for client's chip data, i.e. layout data, while the unit module in the layout data used by the client to be integrated with the IP module contains only a file in the Library Exchange Format (LEF). The LEF file mainly defines the physical information of the unit module, such as cell sizes, geometric shape, route layers, etc. Since the unit module does not have an internal circuit, it is like an IP black box with only connection information and no internal circuits. Before taping out, the IP module needs to be integrated (or incorporated) into the diagram data provided by the client, and the whole process of data integration needs to be carried out by engineers of the foundry. The client mentioned above means the chip designer, and the foundry proceeds to the fabrication of chips with the client's commission; the diagram data and the IP module data are both in GDS format.
Some information about the LEF file needs to be provided for the client during layout design stage, so that the client may proceed to the integration of the IP module according to such information. The information provides the placing and routing tool with knowledge of the processes applied and geometric properties of each layout cells, generally including:
1. Device cell names, cell borders and the coordinates of the origin;
2. Pin names, the metal layer, and the input/output;
3. Other parasitic parameters.
A specific example is given to explain the structure of the LEF diagram. FIG. 1 is the LEF diagram of an existing phase inverter. The diagram includes an input 101 designated by I, an output 102 designated by O, a power supply 103 designated by VSS, a ground terminal 104 designated by GND, where input I is a rectangle, while none of power supply VSS, output O and ground terminal GND is a rectangle.
Before representing the LEF diagram in FIG. 1, various shapes in the diagram need to be segmented into rectangles. As shown in FIG. 2, output 102 in FIG. 1 is segmented with the prior art, where the LEF diagram is segmented according to the coordinates of the vertices of the polygon. And the polygonal structure of output 102 is made up of multiple smaller rectangles. The segment designated by 201 as shown in FIG. 2 represents the smallest rectangular segment. The segmentation method in the prior art enables the representation of the LEF diagram of a polygon with multiple rectangles, but increase the data size of the diagram, which constitutes a problem, as the prior art will make the data size of the LEF diagram of a layout grow continuously with the development of the processes.